Work with cross functional teams to optimize various parts of the SW stack AI Compiler, AI frameworks, device drivers, and firmware. Work on block & system level performance analysis for VLIW based AI Engine processor architecture. Bring up emerging ML models based on CNN, transformers and characterize performance. Develop and validate VLIW based processor systems on both

Work with cross functional teams to optimize various parts of the SW stack AI Compiler, AI frameworks, device drivers, and firmware. Work on block & system level performance analysis for VLIW based AI Engine processor architecture. Bring up emerging ML models based on CNN, transformers and characterize performance. Develop and validate VLIW based processor systems on both

We are looking for a Systems Design Engineer to join the System level Test team in San Jose. You will be involved in the silicon life cycle from testing of emulated next generation RTL through to silicon validation. You will have a view of the full system but also will become an expert in certain IP down to the register level. We are looking for someone who can span the r

Collaborate with architecture, design, product, test, and validation teams for test content coverage, test pattern development, validation, and debug. Architect & develop test software solutions for a wide variety of AMD products to form a complete end to end test solution. Responsible for understanding test challenges and executing large technical projects and processes

Accelerate inference of Generative AI on AMD's products. Develop tools and techniques for model analysis, profiling, performance projections and analyzing architecture bottlenecks. Architect and prototype custom kernels on GPUs and CPUs ( HIP, CUDA, OpenCL, Triton, etc.) Optimize deep learning inference pipeline including graph compilation using AMD AI compilers. Reproduc

Design, implement, and test algorithms for GPU libraries Benchmark, profile and optimize code to maximize throughput on single and multi GPU systems Deliver high quality code and documentation following best practices for open source software development Work with key technical experts across AMD and with our partners and customers to improve ROCm applications, libraries,

Review microarchitectural specifications to analyze hardware IP for potential security weaknesses. Develop a threat model that includes the security scope, potential vulnerabilities, attack vectors, and risk mitigation strategies based on AMD's state of the art security technologies. Develop and implement security verification test plan and define security coverage/sign o

This individual will be responsible for participating and driving large design blocks from early design stage to tapeout. Work responsibilities include synthesizing extremely high speed designs, following through with Place and Route and analyzing design results, and making changes to the RTL code as needed. Work involves daily interaction with other physical designers as

Execute on RTL design and coding for various sections of the processor core pipeline and related logic. Collaborate with a team of hardware and software engineers to define the high level architecture. Participate in the definition of microarchitecture of next generation high performance processor cores. Contribute to design verification, synthesis, power reduction, timin

High Speed PCB Design development Develop routing strategies for new IP including, PCIe, DP, Memory, XGMI Stackup creation and high speed material selection. Strategizing with a variety of teams including, SI, EMI, PI, Thermal and Mechanical Development of Design rules Aiding in the development of New Tools and Processes Developing ASIC ball outs Experience in memory, HDI

Lead hybrid project management teams focused on security improvements for the Instinct GPU line Analyze incoming security vulnerabilities to assess GPU focused product impact and software based mitigation options Engage technical leadership frequently to complete phase gate process for vulnerability assessment and response to external customers/general public Manage Jira

Accelerate inference of Generative AI on AMD's products. Develop tools and techniques for model analysis, profiling, performance projections and analyzing architecture bottlenecks. Architect and prototype custom kernels on GPUs and CPUs (HIP, CUDA, OpenCL, Triton, etc.) Optimize deep learning inference pipeline including graph compilation using AMD AI compilers. Reproduce

Design, and implement high performance runtime features for AIE enabled devices that accelerates ML workloads. Work with technical leads and others to converge on the design of runtime software components. Collaborate with cross functional engineering teams to implement and debug software stack on AIE enabled device as required. PREFERRED EXPERIENCE Strong software develo

Implement working knowledge of principles of logic and transistor level circuit design, CAD tools and expertise in one of many functional areas (e.g., clocks, standard cell libraries, synthesis, place and route, electrical analysis, etc.). Innovate and improve the design. Point out lower power and higher performance tradeoffs. Preparing schedules and scope several months

Support AMD's RCCL, an open source, GPU accelerated communication collective middleware and related technologies Design, implement, and test networking features for multi GPU and multi node communication libraries. Benchmark, profile and optimize code to maximize throughput on single GPU, multi GPU and clustered systems Deliver high quality code and documentation followin